Headline

DV@Broadcom | IIITA | VLSI & Microelectronics

About

DV Engineer with 6 years of experience in Core/IP level verification for various WLAN design blocks at Qualcomm. Currently working on Interrupt IP in Data Fabric team of AMD. HDL: Verilog, System Verilog. HVL : System Verilog and UVM. Tools : Verdi , DVE , Jasper Gold(Formal Verification) Scripting : Perl, Python. I like to excel through smart work, skill set , research and by taking up challenging tasks and responsibilities; with an aim of growth and career advancement. I like to explore about different recent research and development and looking for opportunity in R&D areas.

Location

Bengaluru

AI stack

claude code

Work experience

R&D Engineer IC Design at Broadcom, Nov 2025 - Present · 1 yr, Bengaluru, Karnataka, India

Senior Design Verification Engineer at AMD, Jan 2024 - Nov 2025 · 1 yr 11 mos, Bangalore Urban, Karnataka, India

Senior Design Verification Engineer at Qualcomm, Nov 2022 - Jan 2024 · 1 yr 3 mos, On-site

Design Verification Engineer at Qualcomm, Jun 2020 - Nov 2022 · 2 yrs 6 mos, Bengaluru, Karnataka, India

Education

Electronics and Communications Engineering, Indian Institute Of Information Technology allahabad