---
title: "Chaitali Umarane - Advanced VLSI Design and Verification Trainee in Bengaluru | Tal"
description: "Meet Chaitali Umarane, Aspiring VLSI Engineer | RTL Design & Verification Trainee @Maven Silicon | SystemVerilog | UVM | ECE ’25 based in Bengaluru."
image: "https://tal.club/meet/chaitali-umarane/share-image"
---

# Chaitali Umarane on Tal

## Headline

Aspiring VLSI Engineer \| RTL Design & Verification Trainee @Maven Silicon \| SystemVerilog \| UVM \| ECE ’25

## About

I am a 2025 ECE Graduate and an Advanced VLSI Design & Verification trainee at Maven Silicon with a strong foundation in digital design and verification methodologies\. I have hands\-on experience working with Verilog, SystemVerilog, and UVM, along with a solid understanding of RTL design flow and industry\-standard verification practices\. I am passionate about building reliable verification environments, debugging complex design issues, and ensuring high\-quality functional verification of digital IPs\. 💡 Technical Skills Digital Electronics • Verilog • SystemVerilog • UVM • SVA • QuestaSim • Synopsys VCS • Xilinx ISE • VC SpyGlass Lint • Synopsys Design Compiler 🔧 Projects & Expertise \- Design & Verification of APB to SPI Controller \- Verification of AXI Interconnect Protocol \(AMBA\) using UVM \- Smart Flexible Railway Platform \(Academic Project\) 🎯 Career Objective I am actively seeking a Design Verification Engineer or RTL Design Engineer \(Fresher\) role where I can apply my VLSI skills, contribute to challenging projects, and grow in the semiconductor industry\.

## Location

Bengaluru

## Work experience

Advanced VLSI Design and Verification Trainee at Maven Silicon, Jun 2025 \- Present · 1 yr, Greater Bengaluru Area

## Education

Bachelor of Engineering \- BE, Electronics and Communications Engineering, Visvesvaraya Technological University

[View the original profile](https://tal.club/meet/chaitali-umarane)

```json
{
  "@context": "https://schema.org",
  "@graph": [
    {
      "@type": "Person",
      "@id": "https://tal.club/meet/chaitali-umarane#person",
      "name": "Chaitali Umarane",
      "url": "https://tal.club/meet/chaitali-umarane",
      "image": "https://tal.club/meet/chaitali-umarane/profile-photo.jpg",
      "description": "Meet Chaitali Umarane, Aspiring VLSI Engineer | RTL Design & Verification Trainee @Maven Silicon | SystemVerilog | UVM | ECE ’25 based in Bengaluru.",
      "jobTitle": "Advanced VLSI Design and Verification Trainee",
      "worksFor": {
        "@type": "Organization",
        "name": "Maven Silicon"
      },
      "hasOccupation": {
        "@type": "Occupation",
        "name": "Advanced VLSI Design and Verification Trainee"
      },
      "homeLocation": {
        "@type": "Place",
        "name": "Bengaluru"
      },
      "alumniOf": [
        {
          "@type": "EducationalOrganization",
          "name": "Visvesvaraya Technological University"
        }
      ],
      "mainEntityOfPage": {
        "@id": "https://tal.club/meet/chaitali-umarane#webpage"
      }
    },
    {
      "@type": "ProfilePage",
      "@id": "https://tal.club/meet/chaitali-umarane#webpage",
      "url": "https://tal.club/meet/chaitali-umarane",
      "name": "Chaitali Umarane on Tal",
      "description": "Meet Chaitali Umarane, Aspiring VLSI Engineer | RTL Design & Verification Trainee @Maven Silicon | SystemVerilog | UVM | ECE ’25 based in Bengaluru.",
      "dateModified": "2026-06-10T13:55:53.190Z",
      "isPartOf": {
        "@id": "https://tal.club/#website"
      },
      "mainEntity": {
        "@id": "https://tal.club/meet/chaitali-umarane#person"
      },
      "primaryImageOfPage": {
        "@type": "ImageObject",
        "url": "https://tal.club/meet/chaitali-umarane/profile-photo.jpg",
        "contentUrl": "https://tal.club/meet/chaitali-umarane/profile-photo.jpg",
        "caption": "Chaitali Umarane profile photo on Tal"
      },
      "inLanguage": "en-IN"
    }
  ]
}
```