Aspiring VLSI Engineer | RTL Design & Verification Trainee @Maven Silicon | SystemVerilog | UVM | ECE ’25
Greater Bengaluru Area
Bachelor of Engineering - BE, Electronics and Communications Engineering
Visvesvaraya Technological University
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Download Tal BossAspiring VLSI Engineer | RTL Design & Verification Trainee @Maven Silicon | SystemVerilog | UVM | ECE ’25
I am a 2025 ECE Graduate and an Advanced VLSI Design & Verification trainee at Maven Silicon with a strong foundation in digital design and verification methodologies. I have hands-on experience working with Verilog, SystemVerilog, and UVM, along with a solid understanding of RTL design flow and industry-standard verification practices. I am passionate about building reliable verification environments, debugging complex design issues, and ensuring high-quality functional verification of digital IPs. 💡 Technical Skills Digital Electronics • Verilog • SystemVerilog • UVM • SVA • QuestaSim • Synopsys VCS • Xilinx ISE • VC SpyGlass Lint • Synopsys Design Compiler 🔧 Projects & Expertise - Design & Verification of APB to SPI Controller - Verification of AXI Interconnect Protocol (AMBA) using UVM - Smart Flexible Railway Platform (Academic Project) 🎯 Career Objective I am actively seeking a Design Verification Engineer or RTL Design Engineer (Fresher) role where I can apply my VLSI skills, contribute to challenging projects, and grow in the semiconductor industry.
Bengaluru
Advanced VLSI Design and Verification Trainee at Maven Silicon, Jun 2025 - Present · 1 yr, Greater Bengaluru Area
Bachelor of Engineering - BE, Electronics and Communications Engineering, Visvesvaraya Technological University