---
title: "Chaitali Jagtap - VLSI Design Verification Trainee in Bengaluru | Tal"
description: "Meet Chaitali Jagtap, Aspiring Design Verification Engineer based in Bengaluru."
image: "https://tal.club/meet/chaitali-5/share-image"
---

# Chaitali Jagtap on Tal

## Headline

Aspiring Design Verification Engineer

## About

I have a solid understanding of VLSI design and verification concepts, hands\-on experience with Verilog/SystemVerilog projects, and a strong willingness to learn\. I am hardworking, adaptable, and committed to delivering high\-quality results\. I believe my technical foundation and enthusiasm for Design Verification will allow me to contribute effectively to your team\. I am actively seeking an entry\-level Design Verification role where I can contribute to ASIC/SoC verification teams and grow as a verification engineer

## Location

Bengaluru

## Work experience

VLSI Design Verification Trainee at VLSIGuru Training Institute, Aug 2025 \- Present · 1 yr, Bengaluru, Karnataka, India, • Hands\-on training in RTL design and functional verification using Verilog and SystemVerilog • Designed and verified FIFO and memory modules • Developed SystemVerilog testbenches and executed simulations • Performed debugging using waveform analysis • Worked with FSM\-based designs and verification

## Education

Bachelor of Technology \- BTech, Electronic and communication, Sanjay Ghodawat University

HSC, Kisan Veer Mahavidyalay

[View the original profile](https://tal.club/meet/chaitali-5)

```json
{
  "@context": "https://schema.org",
  "@graph": [
    {
      "@type": "Person",
      "@id": "https://tal.club/meet/chaitali-5#person",
      "name": "Chaitali Jagtap",
      "url": "https://tal.club/meet/chaitali-5",
      "image": "https://tal.club/meet/chaitali-5/profile-photo.jpg",
      "description": "Meet Chaitali Jagtap, Aspiring Design Verification Engineer based in Bengaluru.",
      "jobTitle": "VLSI Design Verification Trainee",
      "worksFor": {
        "@type": "Organization",
        "name": "VLSIGuru Training Institute"
      },
      "hasOccupation": {
        "@type": "Occupation",
        "name": "VLSI Design Verification Trainee"
      },
      "homeLocation": {
        "@type": "Place",
        "name": "Bengaluru"
      },
      "alumniOf": [
        {
          "@type": "EducationalOrganization",
          "name": "Sanjay Ghodawat University"
        },
        {
          "@type": "EducationalOrganization",
          "name": "Kisan Veer Mahavidyalay"
        }
      ],
      "mainEntityOfPage": {
        "@id": "https://tal.club/meet/chaitali-5#webpage"
      }
    },
    {
      "@type": "ProfilePage",
      "@id": "https://tal.club/meet/chaitali-5#webpage",
      "url": "https://tal.club/meet/chaitali-5",
      "name": "Chaitali Jagtap on Tal",
      "description": "Meet Chaitali Jagtap, Aspiring Design Verification Engineer based in Bengaluru.",
      "dateModified": "2026-07-18T05:19:36.752Z",
      "isPartOf": {
        "@id": "https://tal.club/#website"
      },
      "mainEntity": {
        "@id": "https://tal.club/meet/chaitali-5#person"
      },
      "primaryImageOfPage": {
        "@type": "ImageObject",
        "url": "https://tal.club/meet/chaitali-5/profile-photo.jpg",
        "contentUrl": "https://tal.club/meet/chaitali-5/profile-photo.jpg",
        "caption": "Chaitali Jagtap profile photo on Tal"
      },
      "inLanguage": "en-IN"
    }
  ]
}
```