Headline

Aspiring Design Verification Engineer

About

I have a solid understanding of VLSI design and verification concepts, hands-on experience with Verilog/SystemVerilog projects, and a strong willingness to learn. I am hardworking, adaptable, and committed to delivering high-quality results. I believe my technical foundation and enthusiasm for Design Verification will allow me to contribute effectively to your team. I am actively seeking an entry-level Design Verification role where I can contribute to ASIC/SoC verification teams and grow as a verification engineer

Location

Bengaluru

Work experience

VLSI Design Verification Trainee at VLSIGuru Training Institute, Aug 2025 - Present · 1 yr, Bengaluru, Karnataka, India, • Hands-on training in RTL design and functional verification using Verilog and SystemVerilog • Designed and verified FIFO and memory modules • Developed SystemVerilog testbenches and executed simulations • Performed debugging using waveform analysis • Worked with FSM-based designs and verification

Education

Bachelor of Technology - BTech, Electronic and communication, Sanjay Ghodawat University

HSC, Kisan Veer Mahavidyalay