Headline

VLSI Design & Verification Trainee | Verilog | SystemVerilog | UVM | Assertions | Functional Coverage | RTL Design

About

I’m an aspiring VLSI Design and Verification Engineer with strong technical skills and a solid understanding of digital concepts. Digital Electronics: Good understanding of combinational and sequential circuits, FSMs, and timing concepts. Verilog: Hands-on experience in RTL design, simulation, and testbench development. SystemVerilog: Knowledge of OOP concepts, constrained randomization, and assertions. UVM: Familiar with environment creation, sequences, agents, and reusable testbench architecture. I’m passionate about verification methodologies and eager to contribute to innovative semiconductor designs while continuously learning and improving my skills.

Location

Ravula Palem

AI stack

claude code

claude

gemini

hedra

openai

ChatGPT

Work experience

Design and Verification Trainee at Maven Silicon, Nov 2025 - Jul 2026 · 9 mos, Bengaluru, Karnataka, India, Advanced VLSI Design and Verification Trainee • Learned Verilog and SystemVerilog for RTL design and verification. • Developed knowledge of UVM, Assertions, Functional Coverage, and Constrained Random Verification. • Worked on protocol-based verification concepts such as AHB, APB, and UART. • Gained hands-on experience in testbench development and debugging.

Education

Bachelor of Technology, Electrical, Electronics and Communications Engineering, Srinivasa Institute of Engineering & Technology

Intermediate, MPC, Sri chaitanya junior college, Kakinada