Aspiring VLSI Design Engineer | RTL · Verilog HDL · FSM Design | NIT Warangal EEE | INSPIRE MANAK Awardee
Bachelor of Technology - BTech, Electrical and Electronics Engineering
NIT warangal
Join Bhavitha and 10k+ other professionals on
Tal is the app where bosses meet engineers & builders directly, without middlemen
Download Tal BossAspiring VLSI Design Engineer | RTL · Verilog HDL · FSM Design | NIT Warangal EEE | INSPIRE MANAK Awardee
EEE undergraduate at NIT Warangal with hands-on experience in RTL design and verification using Verilog HDL. Built a 16-bit 5-stage pipelined RISC processor with dual forwarding paths and hazard detection. Experienced in FSM-based digital system design, waveform-level verification in GTKWave, and modular RTL architecture. INSPIRE MANAK Awardee — selected among top 42 students statewide for innovation in science.
India
aistudio
dalle
sora
v0
Executive Member at Electrical Engineering Society, NIT Warangal, Aug 2025 - Present · 11 mos
Executive Member at National Service Scheme(NSS), NIT Warangal, Aug 2025 - Present · 11 mos
Member at IEEE SB NITW, Apr 2025 - Present · 1 yr 3 mos
Bachelor of Technology - BTech, Electrical and Electronics Engineering, NIT warangal