---
title: "Bhavana Raj - M.Tech VLSI Design | ASIC Design, UVM Verification & Physical Design (RTL-to-GDSII) | SystemVerilog in India | Tal"
description: "Meet Bhavana Raj, M.Tech VLSI Design | ASIC Design, UVM Verification & Physical Design (RTL-to-GDSII) | SystemVerilog based in India."
image: "https://tal.club/meet/bhavana-8/share-image"
---

# Bhavana Raj on Tal

## Headline

M\.Tech VLSI Design \| ASIC Design, UVM Verification & Physical Design \(RTL\-to\-GDSII\) \| SystemVerilog

## Location

India

## Education

Master of Technology \- MTech, VLSI, Vellore Institute of Technology

Bachelor of Engineering, Electrical, Electronic and Communications Engineering Technology/Technician, Atria Institute of technology

[View the original profile](https://tal.club/meet/bhavana-8)

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