Bharatesh Jain profile photo 1 on Tal

Bharatesh Jain

Staff Design Engineer at ARM

Bengaluru

15+ years of work experience

Arm
Jun 201610 yrs 5 mosPresent

Bengaluru

Responsible for Design, Development, and Delivery of Standard Cell Library IP's.
Design Tech
Nov 20132 yrs 7 mosMay 2016

Bangalore

Currently working on SRAM memory design and characterization in 20nm technology. Working in Dynamic power analysis, leakage current measurements, IR Analysis and sig-EM. Writing spice deck file, simulating power and leakage through HSIM and HSPICE simulator tools. IR Analysis and writing spice deck for power gating switch cell characterization, measuring various parameters like Ion current and resistance. Writing input stimulus for timing and performing memory read and write operations and checking various features of memories. SNM Calculations using the N-curve method.
Interra Systems
Apr 20112 yrs 4 mosJul 2013

Bengaluru, Karnataka, India

Worked on Srandard Cell library development with complete views generation and validation for all view worked on various tech nodes - 40nm, 60nm and 180nm Shell and perl scripting to automate the flow and reduce manual effort for library development activity Involved in new cell design, simulations and debugging issues for functionality check and failures during characterization and views validation.

Bharatesh’s AI Stack

claude code
claude code
claude
claude
gemini
gemini
github copilot
github copilot
Microsoft Copilot
Microsoft Copilot

Education

Visvesvaraya Technological University

Visvesvaraya Technological University

20064 yrs2010

Join Bharatesh and 10k+ other professionals on

Tal Boss

Tal is the app where bosses meet engineers & builders directly, without middlemen

Download Tal Boss

Bharatesh Jain on Tal

Headline

Staff Design Engineer at ARM

Location

Bengaluru

AI stack

claude code

claude

gemini

github copilot

Microsoft Copilot

Work experience

Staff Design Engineer at Arm, Jun 2016 - Present · 10 yrs 5 mos, Bengaluru, Responsible for Design, Development, and Delivery of Standard Cell Library IP's.

Memory Design and Characterization Engineer at Design Tech, Nov 2013 - May 2016 · 2 yrs 7 mos, Bangalore, Currently working on SRAM memory design and characterization in 20nm technology. Working in Dynamic power analysis, leakage current measurements, IR Analysis and sig-EM. Writing spice deck file, simulating power and leakage through HSIM and HSPICE simulator tools. IR Analysis and writing spice deck for power gating switch cell characterization, measuring various parameters like Ion current and resistance. Writing input stimulus for timing and performing memory read and write operations and checking various features of memories. SNM Calculations using the N-curve method.

Design Engineer at Interra Systems, Apr 2011 - Jul 2013 · 2 yrs 4 mos, Bengaluru, Karnataka, India, Worked on Srandard Cell library development with complete views generation and validation for all view worked on various tech nodes - 40nm, 60nm and 180nm Shell and perl scripting to automate the flow and reduce manual effort for library development activity Involved in new cell design, simulations and debugging issues for functionality check and failures during characterization and views validation.

Education

Visvesvaraya Technological University

Bharatesh Jain - Staff Design Engineer in Bengaluru | Tal