---
title: "Balaskanda AV - Advanced VLSI Design and Verification Trainee in Greater Bengaluru Area | Tal"
description: "Meet Balaskanda AV, Electronics Engineering Graduate | Verification Engineer (Fresher) | SystemVerilog, UVM, Functional Verification based in Greater Bengaluru Area. AI stack includes github copilot and ChatGPT."
image: "https://tal.club/meet/balaskanda-av/share-image"
---

# Balaskanda AV on Tal

## Headline

Electronics Engineering Graduate \| Verification Engineer \(Fresher\) \| SystemVerilog, UVM, Functional Verification

## About

👋 Hi, I’m a B\.E ECE graduate with a strong interest in VLSI Design Verification and hands\-on experience in SystemVerilog and UVM\-based verification\. 📘 Core Knowledge: Digital Electronics \| RTL Concepts \| Static Timing Analysis 🛠 Languages & Methodologies: Verilog \| SystemVerilog \| UVM \| Constrained Random Verification \| RAL ⚡ Verification Skills: SystemVerilog Assertions \(SVA\) \| Functional Coverage \| Testbench Development \| Coverage\-Driven Verification 🔗 Protocols: AXI \| AHB \| APB ⚙️ Tools: Synopsys VCS \| Questa \| DC Shell 💡 Project Experience: Built a UVM verification environment for an AXI to AHB Bridge IP, where I developed test scenarios, validated protocol compliance, and identified functional and corner\-case bugs\. 🎯 Career Goal: To start my career as a Verification / UVM Engineer, contributing to reliable verification environments and helping deliver high\-quality, first\-time\-right silicon\.

## Location

Greater Bengaluru Area

## AI stack

github copilot

ChatGPT

## Work experience

Advanced VLSI Design and Verification Trainee at Maven Silicon, Feb 2025 \- Feb 2026 · 1 yr 1 mo, Bengaluru, Karnataka, India, • Undergone industry\-oriented training in SystemVerilog and UVM\-based functional verification following front\-end ASIC verification flows\. • Built reusable UVM testbenches, including sequencer, driver, monitor, scoreboard, and coverage components\. • Performed UVM\-based verification of an AXI to AHB Bridge IP, where the RTL \(DUT\) was provided and I owned the verification responsibility\. • Verified AXI/AHB protocol compliance, including handshaking, burst transactions, reset behavior, and corner cases using constrained\-random testing\. • Implemented SystemVerilog Assertions \(SVA\) and functional coverage \(covergroups & coverpoints\) to support verification closure\. • Used Synopsys VCS, Questa, and DC Shell for simulation, debugging, and verification analysis\. • Focused on identifying functional and protocol\-level bugs and improving overall test coverage\.

Intern at Rooman Technologies, Nov 2024 \- Jan 2025 · 3 mos, Bengaluru South, Karnataka, India, Cloud Application Developer

Design Engineering Intern at AISEMI PRIVATE LIMITED, Nov 2023 \- Nov 2023 · 1 mo, Bengaluru, • Gained industry\-oriented exposure to VLSI fundamentals, including digital design concepts, RTL design basics, and verification workflows\. • Introduced to Verilog/SystemVerilog, simulation flow, and the role of verification in ASIC development\. • Learned the end\-to\-end VLSI design cycle, from specification understanding to design, verification, and tape\-out overview\. • Observed and understood RTL coding standards, debugging practices, and waveform\-based analysis\. • Developed foundational understanding of ASIC vs FPGA flows, synthesis, and verification methodologies\. • Strengthened interest in VLSI and functional verification, which later led to advanced UVM\-focused training

## Education

Bachelor of Engineering \- BE, Electrical, Electronics and Communications Engineering, Rajarajeswari College of Engineering\(RRCE\)

2nd PU, Physics, Chemistry, Mathematics & Computer Science, JAIN College

[View the original profile](https://tal.club/meet/balaskanda-av)

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