---
title: "Balaraj S A - Cloud R&D Engineering Intern in Bengaluru | Tal"
description: "Meet Balaraj S A, RTL Design & Verification Engineer | SystemVerilog · FPGA | RISC-V Processor Designer | Synopsys VCS · Xilinx Vivado | ECE 2026 | VLSI Front-End based in Bengaluru. AI stack includes antigravity, codex, and github copilot."
image: "https://tal.club/meet/balaraj-s-a/share-image"
---

# Balaraj S A on Tal

## Headline

RTL Design & Verification Engineer \| SystemVerilog · FPGA \| RISC\-V Processor Designer \| Synopsys VCS · Xilinx Vivado \| ECE 2026 \| VLSI Front\-End

## About

I am an Electronics and Communication Engineering graduate passionate about RTL design, FPGA development, and digital hardware systems\. I enjoy transforming digital design concepts into working hardware through RTL implementation, functional verification, FPGA prototyping, and hardware validation\. My experience includes designing and verifying digital systems using Verilog and SystemVerilog, implementing RISC\-V processor enhancements with custom in\-memory computing extensions, developing SystemVerilog verification environments, and prototyping designs on PYNQ\-Z2 and Basys3 FPGA platforms\. I have also worked on real\-time HDMI video processing, hardware validation, and embedded system projects involving Raspberry Pi and Arduino\. During my internships at Ellucian and Kaynes Technology, I gained exposure to collaborative engineering environments, product development workflows, hardware validation, debugging, and technical documentation\. I am actively seeking opportunities in RTL Design, FPGA Engineering, ASIC Front\-End Design, Digital Design, Functional Verification, and RISC\-V development, where I can continue learning and contribute to innovative semiconductor products\. Core Skills: RTL Design • SystemVerilog • Verilog • FPGA Prototyping • Functional Verification • RISC\-V • Xilinx Vivado • Synopsys VCS • Static Timing Analysis \(STA\) • Hardware Validation • Embedded Systems

## Location

Bengaluru

## AI stack

antigravity

codex

github copilot

openai

## Work experience

Cloud R&D Engineering Intern at Ellucian, Feb 2026 \- Jun 2026 · 5 mos, Bengaluru, Karnataka, India, Embedded within a professional R&D engineering team, contributing to software product feature development and engineering team workflows in an enterprise technology company\. \.• Contributed to product development and technical documentation within a collaborative engineering team\. • Automated routine engineering workflows using scripting to improve development efficiency\. • Worked in an Agile engineering environment, collaborating across cross\-functional teams\.

Research And Development Intern at Ellucian, Feb 2026 \- May 2026 · 4 mos, Contributed to product research, development, and technical documentation within a collaborative engineering team\. Automated routine workflow tasks using scripting and gained exposure to product development practices\.

Hardware Validation Engineer Intern Company: Kaynes Technology Inc — ISKRAEMECO Division at Kaynes Technology Inc, Feb 2023 \- Jun 2023 · 5 mos, Mysore, Karnataka, India, • Performed board\-level validation and functional testing of smart energy meter hardware\. • Conducted NIC testing, hardware debugging, and defect reporting during validation activities\. • Collaborated with engineering teams to analyze failures and document test results\.

## Education

Bachelor of Engineering \- BE, Electronic and Communications Engineering, B\. M\. S\. College of Engineering

Diploma of Education, Electronics and Communications Engineering, Government Polytechnic college

[View the original profile](https://tal.club/meet/balaraj-s-a)

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