Headline

VLSI Engineer | Post-Silicon Validation

About

VLSI and Post-Silicon Validation Engineer with 4.8+ years of experience specializing in DUT bring-up, Platform debugging, and reliability testing. Currently consulting for an industry-leading AI computing giant at Wipro, following a 4+ year tenure at UST driving system validation for a global microprocessor manufacturer. Armed with B.E in ECE, I possess strong architectural knowledge of X86 and ARM. I am highly skilled in debugging complex hardware-software interactions using Linux utilities, Python automation and low level debuggers (Intel DCI, JTAG, Protocol Analyzers). From validating high-speed SoC interfaces(PCIe, USB4, DP etc.) to verifying intricate S0ix/ Sx power state and thermal setups, I am driven by delivering highly stable, production ready platforms.

Location

Bengaluru

Work experience

VLSI Engineer at Wipro, Apr 2026 - Present · 5 mos, Bengaluru, Karnataka, India

Associate 2 - Semiconductor Product Validation Engineer at UST, Oct 2021 - Mar 2026 · 4 yrs 6 mos, Bengaluru, Karnataka, India, • Performed system-level validation and bring-up of platforms, ensuring stability across hardware, firmware, BIOS, and operating system layers. • Validated PCIe-based devices (Thunderbolt controllers, storage, expansion cards) focusing on link training, enumeration, bandwidth, and error handling. • Conducted Linux and Windows-based validation, analysing system logs (Event Viewer), driver behaviour, and device enumeration issues. • Executed stress, soak, and long-duration stability testing to identify reliability, thermal, and power-related failures under sustained workloads. • Performed failure reproduction and root cause analysis for system crashes, performance degradation, and hardware enumeration failures. • Validated power delivery, power sequencing, and power limit behaviour under various load and corner-case scenarios. • Conducted thermal and power characterization under server-like workloads, identifying throttling, power capping, and thermal limit issues. • Used hardware and firmware debug tools (Intel DCI, Trace32, JTAG, protocol analyzers) to isolate silicon, BIOS, and firmware issues. • Analysed hardware error logs and traces to debug protocol, timing, and interoperability issues. • Designed and executed manual and automated validation test cases for regression, feature validation, and system stability. • Automated validation workflows using Python scripts integrated into CI/CD pipelines, reducing manual testing effort and improving coverage. • Collaborated with OEMs and platform teams to validate system integration, compatibility, and readiness for production release. Authored detailed validation reports, bug tickets, and debug documentation, validating fixes and confirming issue closure.

Education

Bachelor of Engineering, Electrical, Electronics and Communications Engineering, Rajalakshmi Engineering college