---
title: "Avinash Raina - Design Verification Engineer in Bengaluru | Tal"
description: "Meet Avinash Raina, Digital Design Engineer based in Bengaluru. AI stack includes claude code, claude, and gemini."
image: "https://tal.club/meet/avinash-raina/share-image"
---

# Avinash Raina on Tal

## Headline

Digital Design Engineer

## About

Deep interest in vlsi design and embedded systems\.Looking for best oppurtunities in the field of electronics\.

## Location

Bengaluru

## AI stack

claude code

claude

gemini

openai

claudecode

ChatGPT

## Work experience

Design Verification Engineer at Texas Instruments India, Jul 2024 \- Present · 2 yrs 5 mos, Bengaluru, Drove functional verification for 6\+ SoC IPs: GPADC, Memory Protection Unit \(MPU\), Reset & Clock Manager \(RCM\), Memory Map, and IAGR, collaborating with RTL, architecture, and cross\-functional teams\. Achieved 95%\+ code coverage and 100% toggle coverage signoff, ensuring comprehensive verification closure across all owned IPs prior to tape\-out\. Identified and resolved 20\+ RTL bugs during pre\-silicon verification, directly reducing post\-silicon debug cycles and engineering rework\. Pioneered an AI\-assisted framework \(Claude LLM \+ custom Python automation\) to auto\-generate and port 100\+ MPU verification testcases across derivative SoC projects\. Reduced testcase porting time by \~70%, eliminated manual migration errors, ensured cross\-project verification consistency, and accelerated project bring\-up timelines\. Established a scalable SVA library covering functional, architectural, and timing requirements\. Developed and deployed following assertion categories: Glitch detection assertions, Clock frequency validation assertions, Hard\-macro unknown state checks based assertions, Memory state integrity assertions\. Automated assertion generation and cross\-project deployment, improving regression quality and preventing recurrence of 10\+ previously observed silicon issues\. Owned Memory Map and IAGR verification at project start, validating register accessibility, address decoding correctness, and peripheral R/W behavior against Magillem\-generated specifications\. Enabled early detection of 15\+ specification and RTL inconsistencies, reducing downstream integration debug effort before functional verification commenced\. Designed and implemented an automated reverse\-connectivity verification flow using Cadence JasperGold to detect missing or unintended RTL signal connections across SoC\. Reduced manual connectivity review effort by \~60%, strengthened RTL signoff confidence, and prevented potential connectivity\-related silicon failures\.

Digital Design Engineer at Texas Instruments India, Jan 2024 \- Jun 2024 · 6 mos, Bengaluru, Karnataka, India

Design Engineering Intern at Texas Instruments India, Jan 2024 \- Jun 2024 · 6 mos, Designed and implemented a scalable UVM verification environment for SoC interconnect, automating key components: environment setup, scoreboard, testbenches, and sequences\. Reduced interconnect DV build effort by \~50% compared to manual approach, improving reusability and scalability across derivative SoC projects\.

## Education

ME, Embedded Systems, Birla Institute of Technology and Science, Pilani

Bachelor of Technology \- BTech, Electrical, Electronics and Communications Engineering, University School of Information, Communication & Technology \(USICT\)

[View the original profile](https://tal.club/meet/avinash-raina)

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