Headline

RTL Design Engineer | ASIC Front-End | FPGA Synthesis | Verilog/SystemVerilog | RISC-V | Digital Design

About

RTL Design Engineer skilled in Verilog/SystemVerilog, FPGA synthesis, and ASIC front-end design. Experienced in building and verifying digital circuits (ALU, FIFO, cache controllers, UART, pipelined RISC-V cores, and a 64-bit accelerator) with measurable performance gains in both simulation and FPGA prototyping. Strong background in semiconductor devices and nanotechnology, with hands-on expertise in RTL/ASIC design principles, testbench development, and hardware verification.

Location

Gurugram

AI stack

claude code

cursor

obsidian

AssemblyAI

FLUX

Work experience

Jr. Hardware Engineer at Quin, Dec 2025 - Present · 11 mo, Hyderabad, Telangana, India, Hardware engineer on a wearable crash-detection sensor, owning the board from design through validation, plus the technical side of regulatory compliance for EU, US, and Australian markets. Hardware design and validation • Own schematic design and PCB layout in Altium Designer, from IC selection and BOM through gerber output and manufacturing handoff • Lead bring-up and debug of prototype and pilot boards, including sensor self-test verification and interface-level debugging across I²C, SPI, and UART • Validate firmware integration for sensor-driven devices: decode and verify high-rate IMU, impact, and telemetry data over BLE using Python analysis pipelines, covering bit-level parsing, signed data interpretation, FIFO sequencing, and timestamp integrity • Debug data leakage between operating modes, payload inconsistencies, and buffer misalignment by mapping raw hex streams to firmware behaviour • Build reliable test workflows and run system-level validation Technical compliance • Lead hardware-side compliance across the EU Battery Regulation (2023/1542), RED, Cyber Resilience Act, California SB 1215, and Australian RCM, and track new rules such as the EU Data Act • Compile technical evidence and documentation for partners, validate component certifications (UN38.3, IEC 62133-2), and work with external legal and technical advisers

Research Apprentice at SRM University, Jan 2022 - May 2025 · 3 yrs 5 mos, Chennai, Tamil Nadu, India, Modeled and simulated NiO and Mg-doped NiO processors in COMSOL Multiphysics to study material-level effects on processor performance. •Analyzed 3 samples (pure NiO, 2% Mg-doped, 4% Mg-doped) and observed ~15–20% improvement in conductivity and switching efficiency with Mg doping. •Conducted parametric simulations on thermal stability, bandgap variation, and carrier transport. •Documented results for thesis and research presentations, strengthening expertise in semiconductor materials, device physics, and simulation tools.

Education

Bachelor of Technology - BTech, Nanotechnology, SRM Institute of Science and Technology (SRMIST)

St Andrews High School, Suchitra