---
title: "Avadhesh Kumar Verma - Design Verification Engineer – AI/Compute Subsystems in Bengaluru | Tal"
description: "Meet Avadhesh Kumar Verma, Design Verification Engineer | AI Compute Subsystems | Qualcomm | IIT Delhi M.Tech’24 based in Bengaluru. AI stack includes claude code, claude, and gemini."
image: "https://tal.club/meet/avadhesh-kumar-verma/share-image"
---

# Avadhesh Kumar Verma on Tal

## Headline

Design Verification Engineer \| AI Compute Subsystems \| Qualcomm \| IIT Delhi M\.Tech’24

## About

Design Verification Engineer working on advanced AI compute subsystems for Qualcomm SoCs\. As part of a subsystem\-level Design Verification team, I contribute to the pre\-silicon verification and functional debug of complex compute hardware supporting AI, multimedia, signal\-processing, and other high\-throughput workloads\. My experience spans multiple critical areas of hardware verification, including RTL analysis, block and subsystem integration, functional verification, clock\-domain crossing verification, and Fishtail verification of false paths and multi\-cycle paths\. I have also worked on memory redundancy verification, formal connectivity verification, coverage development, test\-case development, power\-related sequence updates, regression analysis, and failure triage\. My work also includes analyzing simulation and formal results, investigating functional failures, debugging RTL and subsystem behavior, and collaborating with design, architecture, and verification teams to perform root\-cause analysis and improve verification quality and readiness\. In addition to core verification activities, I have contributed to verification automation, including regression monitoring and an AI\-assisted debug and triage agent\. These tools support my primary focus in design verification by improving failure analysis efficiency and reducing debug time\. Areas of expertise and interest: • Design Verification and Pre\-Silicon Verification • Subsystem Verification • RTL analysis and functional debug • CDC Verification • Fishtail Verification • Memory Redundancy Verification • Formal Connectivity Verification • Functional Coverage & Testcase Development • Regression Analysis and Failure Triage • Power\-Aware Verification and Sequence Development • Verification Automation and Scripting

## Location

Bengaluru

## AI stack

claude code

claude

gemini

## Work experience

Design Verification Engineer – AI/Compute Subsystems at Qualcomm, Jul 2024 \- Present · 2 yrs 2 mos, Bengaluru, Karnataka, India, • Contributed to pre\-silicon design verification of AI compute subsystems for Qualcomm SoCs\. • Worked on RTL analysis, functional verification, test\-case and coverage development, regression analysis, and failure triage\. •Performed CDC, formal connectivity, memory redundancy, and Fishtail verification for false paths and multi\-cycle paths\. •Developed and updated power\-aware verification sequences and analyzed clock, reset, memory, interconnect, and control\-path behavior\. • Collaborated with design and verification teams on root\-cause analysis, debug, and verification\-quality improvement\. • Supported verification automation through regression monitoring and an AI\-assisted debug and triage solution\.

## Education

Master of Technology \- MTech, Indian Institute of Technology, Delhi

Bachelor of Technology \- BTech, Jss Academy of Technical Education

[View the original profile](https://tal.club/meet/avadhesh-kumar-verma)

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