Headline

Electronics and communication engineering, Aspiring vlsi engineer

About

Detail-oriented Analog Layout Engineer with knowledge of CMOS and FinFET layout design using Cadence tools. Skilled in DRC, LVS, parasitic extraction, routing, floorplanning, and layout optimization. Familiar with analog blocks like current mirrors, differential pairs, and NAND gates. Strong understanding of VLSI design flow and semiconductor basics. Quick learner, adaptable team player, and eager to contribute to semiconductor and analog IC development projects.

Location

Bengaluru

Work experience

Analog Design Engineer at Advaith innovation and incubation foundation, Feb 2026 - Present · 5 mos, Kolar, Karnataka, India, I am an Electronics and communication Engineering student currently interning as an Analog Layout Engineer at [Advaith innovation and incubation foundation ], where I am gaining hands-on experience in full-custom IC physical design using Cadence Virtuoso. My work involves drawing analog layouts, performing DRC and LVS checks, implementing matching techniques, and collaborating with design engineers to meet layout specifications. I am passionate about analog and mixed-signal IC design and am actively looking for full-time opportunities as an Analog Layout Engineer to further grow my skills and contribute to impactful designs.

Education

Vision India pu college

Sri g g venu Gurukula