Headline

SoC Design Verification Engineer @ Intel | SystemVerilog | UVM | UVM RAL | SVA | Functional Coverage | M.Tech VLSI

About

I am a SoC Design Verification Engineer at Intel with experience in developing and supporting verification environments for complex SoC designs. My core experience includes SystemVerilog, UVM, UVM RAL, functional coverage, assertions, testbench development and verification methodology. I currently work with UVM Register Abstraction Layer (RAL) and have experience contributing to register verification infrastructure in a large-scale SoC environment. I hold an M.Tech in VLSI & Embedded Systems from DIAT, DRDO, where my thesis focused on SoC testbench infrastructure and register verification using UVM RAL. I am particularly interested in SoC/ASIC Design Verification, Pre-Silicon Verification and Validation, and building robust verification environments for complex semiconductor designs. Technical interests: SystemVerilog | UVM | UVM RAL | SVA | Functional Coverage | SoC Verification | Pre-Silicon Verification | ASIC Verification Always interested in connecting with engineers, technical leaders and semiconductor professionals working in these areas.

Location

Greater Bengaluru Area

AI stack

claude code

claude

Work experience

SoC Design Verification Engineer at Intel Corporation, Jun 2024 - Aug 2026 · 2 y 2 mo, Bengaluru

Graduate Intern Technical at Intel Corporation, Aug 2023 - Jun 2024 · 11 mos, Bangalore Urban, Karnataka, India

Citizen Scientist (IASC) at NASA - National Aeronautics and Space Administration, Aug 2021 - Aug 2021 · 1 mo

Research Intern at Defence Research and Development Organisation (DRDO), Jun 2019 - Jul 2019 · 2 mos, New Delhi Area, India

Education

M. Tech, VLSI and Embedded System, Defence Institute of Advanced Technology (DIAT), DU, DRDO

Bachelor of Technology - BTech, Electronics and Communications Engineering, Maharaja Surajmal Institute Of Technology