Arpith Jacob profile photo 1 on Tal

Arpith Jacob

Tech Lead and Manager (SWE) at Google

Mountain View

16+ years of work experience

Google
Nov 20232 yrs 8 mosPresent

Google
Sep 20212 yrs 2 mosOct 2023

Google
Jan 20183 yrs 8 mosAug 2021

Tech Lead and Manager of a team developing an accelerator and compiler (XLA) for key machine learning workloads with immense impact within Google. Co-architect of a domain-specific accelerator for distributed-scale Embeddings. Invented efficient parallel algorithms for training Embeddings on large numbers of cores. Key technique was to invent high-level [X] Linear Algebra primitives that can be optimized by a compiler vs. the traditional approach of stitching library routines. Built and lead a large, diverse team to develop a compiler based on XLA (HLO), MLIR and LLVM to deliver a complete solution to high-value customers. I enjoy working on risky projects with a long timeframe at the intersection of computer architecture, parallel algorithms, compilers, and performance analysis. My value is in working across team boundaries to solve challenging technical problems. My work includes assessing risks and proposing mitigations, detailed planning, and working closely with team members to execute effectively.
IBM
Oct 20134 yrs 4 mosJan 2018

New York City Metropolitan Area

- Building compilation technology for next-generation DoE supercomputers using the LLVM compilation infrastructure. Mapping fork-join parallelism of the OpenMP programming model onto NVIDIA GPUs to exploit the many-threaded SIMT architecture. Designed state-of-the-art code generation scheme using named barriers and warp synchronous model. - Software pipelining of loops for processor-in-memory. Extended swing modulo scheduling for exposed pipeline architecture optimizing memory bandwidth and latency; performing on-the-fly rematerialization and register & memory spilling with backtracking. Code developed in IBM’s XLC production compiler.
IBM
Feb 20112 yrs 9 mosOct 2013

New York City Metropolitan Area

- Code generation within polyhedral framework for hybrid CPU-FPGA accelerators. Generates custom systolic arrays and I/O management in VHDL from C loop programs. Exploits and extends XLC’s polyhedral analyser. - Proposed novel programming abstraction and accelerator hardware for graph analytics. Implemented architectural simulator/
Lawrence Livermore National Laboratory
Jun 20073 mosAug 2007

- Used bloom filters to accelerate n-gram based language classification. - Implemented and tested on XtremeData FPGA system in four weeks. - Wrote Smith-Waterman alignment hardware and software for Netezza database system.
SCM Microsystems
Jun 20031 yr 1 moJun 2004

- Developer of access control terminal providing authentication using smartcards. - Ported uClinux to a Samsung ARM7 processor and wrote device drivers for I2 C interface and smartcard chip. - Experienced in uClinux kernel, bootloaders, JTAG, and smartcard protocols.

Education

Washington University in St. Louis

Ph.D., Computer Science

Washington University in St. Louis

20064 yrs2010
Washington University in St. Louis

Masters, Computer Science

Washington University in St. Louis

20042 yrs2006

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Headline

Tech Lead and Manager (SWE) at Google

Location

Mountain View

Work experience

Senior Staff Software Engineer at Google, Nov 2023 - Present · 2 yrs 8 mos

Staff Software Engineer at Google, Sep 2021 - Oct 2023 · 2 yrs 2 mos

Senior Software Engineer at Google, Jan 2018 - Aug 2021 · 3 yrs 8 mos, Tech Lead and Manager of a team developing an accelerator and compiler (XLA) for key machine learning workloads with immense impact within Google. Co-architect of a domain-specific accelerator for distributed-scale Embeddings. Invented efficient parallel algorithms for training Embeddings on large numbers of cores. Key technique was to invent high-level [X] Linear Algebra primitives that can be optimized by a compiler vs. the traditional approach of stitching library routines. Built and lead a large, diverse team to develop a compiler based on XLA (HLO), MLIR and LLVM to deliver a complete solution to high-value customers. I enjoy working on risky projects with a long timeframe at the intersection of computer architecture, parallel algorithms, compilers, and performance analysis. My value is in working across team boundaries to solve challenging technical problems. My work includes assessing risks and proposing mitigations, detailed planning, and working closely with team members to execute effectively.

Research Staff Member at IBM, Oct 2013 - Jan 2018 · 4 yrs 4 mos, New York City Metropolitan Area, - Building compilation technology for next-generation DoE supercomputers using the LLVM compilation infrastructure. Mapping fork-join parallelism of the OpenMP programming model onto NVIDIA GPUs to exploit the many-threaded SIMT architecture. Designed state-of-the-art code generation scheme using named barriers and warp synchronous model. - Software pipelining of loops for processor-in-memory. Extended swing modulo scheduling for exposed pipeline architecture optimizing memory bandwidth and latency; performing on-the-fly rematerialization and register & memory spilling with backtracking. Code developed in IBM’s XLC production compiler.

Postdoctoral Researcher at IBM, Feb 2011 - Oct 2013 · 2 yrs 9 mos, New York City Metropolitan Area, - Code generation within polyhedral framework for hybrid CPU-FPGA accelerators. Generates custom systolic arrays and I/O management in VHDL from C loop programs. Exploits and extends XLC’s polyhedral analyser. - Proposed novel programming abstraction and accelerator hardware for graph analytics. Implemented architectural simulator/

Student Research Scholar at Lawrence Livermore National Laboratory, Jun 2007 - Aug 2007 · 3 mos, - Used bloom filters to accelerate n-gram based language classification. - Implemented and tested on XtremeData FPGA system in four weeks. - Wrote Smith-Waterman alignment hardware and software for Netezza database system.

Software Engineer at SCM Microsystems, Jun 2003 - Jun 2004 · 1 yr 1 mo, - Developer of access control terminal providing authentication using smartcards. - Ported uClinux to a Samsung ARM7 processor and wrote device drivers for I2 C interface and smartcard chip. - Experienced in uClinux kernel, bootloaders, JTAG, and smartcard protocols.

Education

Ph.D., Computer Science, Washington University in St. Louis

Masters, Computer Science, Washington University in St. Louis