---
title: "Aravinda Kishora Bramha G - Design Verification Engineer in Bengaluru | Tal"
description: "Meet Aravinda Kishora Bramha G, -- based in Bengaluru. AI stack includes claude code and claude."
image: "https://tal.club/meet/aravinda-kishora/share-image"
---

# Aravinda Kishora Bramha G on Tal

## Headline

\-\-

## Location

Bengaluru

## AI stack

claude code

claude

## Work experience

Design Verification Engineer at MediaTek, Oct 2024 \- Present · 1 yr 11 mos, Bengaluru, Worked on Common and Multimedia Bus IP’s Verified multiple IP’s handling protocol transfer between AHB,APB and AXI involving cross\-protocol communication, asynchronous transfer and arbitration\. Ensured functional safety design features compliance through extensive scenario creation and implementation of checkers/assertions for multiple IP’s Developed UVM testbench architecture from scratch for APB\-based IP for an automotive project\. Worked on AXI/APB protocol verification in automotive projects\. Achieved 100% functional coverage closure for automotive APB IP verification\. Experience with assertions, functional coverage, and protocol compliance verification\.

Project Intern at Atria Logic Inc\., Feb 2023 \- Aug 2023 · 7 mos, Tirupati, Andhra Pradesh, India

Internship Trainee at Atria Logic Inc\., Feb 2023 \- Aug 2023 · 7 mos, On\-site

## Education

Master of Technology, Electrical, Electronics and Communications Engineering, Birla Institute of Technology and Science, Pilani

Professional Training, Advanced VLSI Design and Verification, Maven Silicon

[View the original profile](https://tal.club/meet/aravinda-kishora)

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