Aravinda Kishora Bramha G profile photo 1 on Tal

Aravinda Kishora Bramha G

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Bengaluru

2+ years of work experience

MediaTek
Oct 20241 yr 11 mosPresent

Bengaluru

Worked on Common and Multimedia Bus IP’s Verified multiple IP’s handling protocol transfer between AHB,APB and AXI involving cross-protocol communication, asynchronous transfer and arbitration. Ensured functional safety design features compliance through extensive scenario creation and implementation of checkers/assertions for multiple IP’s Developed UVM testbench architecture from scratch for APB-based IP for an automotive project. Worked on AXI/APB protocol verification in automotive projects. Achieved 100% functional coverage closure for automotive APB IP verification. Experience with assertions, functional coverage, and protocol compliance verification.
Atria Logic Inc.
Feb 20237 mosAug 2023

Tirupati, Andhra Pradesh, India

Atria Logic Inc.
Feb 20237 mosAug 2023

On-site

Aravinda’s AI Stack

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Education

Birla Institute of Technology and Science, Pilani

Master of Technology, Electrical, Electronics and Communications Engineering

Birla Institute of Technology and Science, Pilani

20252 yrs2027

Professional Training, Advanced VLSI Design and Verification

Maven Silicon

20231 yr2024

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Aravinda Kishora Bramha G on Tal

Headline

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Location

Bengaluru

AI stack

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Work experience

Design Verification Engineer at MediaTek, Oct 2024 - Present · 1 yr 11 mos, Bengaluru, Worked on Common and Multimedia Bus IP’s Verified multiple IP’s handling protocol transfer between AHB,APB and AXI involving cross-protocol communication, asynchronous transfer and arbitration. Ensured functional safety design features compliance through extensive scenario creation and implementation of checkers/assertions for multiple IP’s Developed UVM testbench architecture from scratch for APB-based IP for an automotive project. Worked on AXI/APB protocol verification in automotive projects. Achieved 100% functional coverage closure for automotive APB IP verification. Experience with assertions, functional coverage, and protocol compliance verification.

Project Intern at Atria Logic Inc., Feb 2023 - Aug 2023 · 7 mos, Tirupati, Andhra Pradesh, India

Internship Trainee at Atria Logic Inc., Feb 2023 - Aug 2023 · 7 mos, On-site

Education

Master of Technology, Electrical, Electronics and Communications Engineering, Birla Institute of Technology and Science, Pilani

Professional Training, Advanced VLSI Design and Verification, Maven Silicon