---
title: "APURVA SMITA - Intern in Dhanbad-Ranchi Area | Tal"
description: "Meet APURVA SMITA, IEEE Published | UVM Verification | CDC | RTL Design | Low-Power Analog | Standard Cell | STA | BIT Mesra MTech VLSI 2026 | Open to Work based in Dhanbad-Ranchi Area. AI stack includes hugging face, ollama, and openai. Explore public work links including github."
image: "https://tal.club/meet/apurva-smita/share-image"
---

# APURVA SMITA on Tal

## Headline

IEEE Published \| UVM Verification \| CDC \| RTL Design \| Low\-Power Analog \| Standard Cell \| STA \| BIT Mesra MTech VLSI 2026 \| Open to Work

## About

IEEE\-published M\.Tech VLSI Graduate from BIT Mesra\(CGPA 8\.34 \| Merit Scholar\), specializing in UVM\-based Design Verification, CDC Analysis, and Low\-Power Analog IC Design with zero verification failures across all projects\. Proficient in building complete UVM testbench environments with Agents, Sequencers, Drivers,Monitors, Scoreboards, TLM, SVA checkers, Constrained Random Testing, Functional Coverage, and Assertion\-Based Verification \(ABV\)\. Hands\-on experience in RTL Design,Clock Domain Crossing \(CDC\), Gray\-Code Synchronization, Metastability Analysis, and Analog IC Design using Cadence Virtuoso/Spectre \(90nm\)\. Co\-authored an IEEE paper \(ISED 2025\) on a custom 32\-bit RISC\-V processor\. Completed HDLBits Verilog 100%\. Seeking roles in: Design Verification Engineer\|Functional Verification Engineer\|SoC Verification Engineer\|IP Verification Engineer\|Hardware Verification Engineer\|RTL Design & Verification Engineer\|Analog/Mixed\-Signal Verification Engineer\|Embedded System Engineer

## Location

Dhanbad\-Ranchi Area

## AI stack

hugging face

ollama

openai

replit

## Work experience

Intern at Doordarshan Kendra, Aug 2023 \- Sep 2023 · 2 mos, Pursued 6 weeks Training Doordarshan Kendra where I became familiar with various technical areas concerning, T\.V\. broadcasting such as MSR, TV studio chain, uplink downlink chains, terrestrial broadcasting, news production and transmission\.

## Education

M\.Tech in VLSI Design and Embedded System, Electronics and Communications Engineering, Birla Institute of Technology, Mesra

B\.E\. in Electronics and Communication Engineering, R\.N\.S Institute of Technology

## Public links

- github: https://github\.com/apurva\-smita

[View the original profile](https://tal.club/meet/apurva-smita)

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