C++ Developer HMS||.Ex- Research intern DIAT -DRDO

On-site

Pune District, Maharashtra, India
Pune

Pune District, Maharashtra, India

Pune/Pimpri-Chinchwad india







Electrical, Electronics and Communications Engineering
Savitribai Phule Pune University
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Junior Firmware Engineer at HMS Networks, Jun 2024 - Present · 2 yrs 3 mos, On-site, • Built the client-side OPC UA communication stack (open62541, C++17/23) that connects industrial devices to SCADA/IoT systems over embedded Linux. •Redesigned channel handling to a one-thread-per-channel model using POSIX threads and mutex-protected state, cutting communication downtime by ~32% under sustained load. •Built a certificate lifecycle service (generation, renewal, revocation) in Python integrated with AWS IoT Core, enabling secure automated device provisioning at scale. •Hardened device identity using the SE050 secure element for key generation and entropy alongside mbedTLS-based RSA/ECC session security, closing a key-extraction attack surface on industrial network links.
Graduate Engineering Trainee at HMS Networks, Aug 2023 - May 2024 · 10 mos, Pune District, Maharashtra, India, • Delivered ESP32-S3 HMI firmware (Qt + FreeRTOS), including SPI display driver bring-up and UART-based field debugging tooling. • Tuned RTOS task scheduling and mutex usage to bring display-trigger response time under 2ms, improving perceived UI responsiveness. • Brought up the Wi-Fi driver as part of a hardware migration from ESP32-S2 to ESP32-S3, including WPA2/WPA3 event-driven connection handling on the new SoC. • Implemented MISRA-compliant state-retention logic on STM32 using Flash/RAM persistence, so device configuration survives power loss.
Research Intern at Defense Institute of Advanced Technology (DIAT), DU, DRDO, May 2023 - Aug 2023 · 4 mos, Pune, • Implemented FMCW radar chirp generation and signal capture for an L-band radar prototype using a USRP B210 SDR and GNU Radio. • Reduced chirp-timing jitter from ~5ms to ~1ms by applying CPU core isolation on the USRP B210 host, removing scheduling interference from the timing-critical signal path. • Published A paper on developement of L band FMCW radar at 2024 Second International Conference on Emerging Trends in Information Technology and Engineering (ICETITE)
Machine Learning Intern at TE Connectivity, Oct 2022 - May 2023 · 8 mos, Pune District, Maharashtra, India, Developed a Sales Forecasting model using statistics and ML
Electronics Engineering Intern at Klutch Bikes, Jun 2021 - Jun 2022 · 1 yr 1 mo, Pune/Pimpri-Chinchwad india, • Owned ECU firmware development for an electric-bicycle motor control unit — from schematic review and BOM creation through board bring-up and integration testing. • Interfaced a 3-phase motor controller with a Teensy (ARM Cortex-M) microcontroller to drive real-time motor control and throttle response. • Consolidated a multi-board control design into a single control unit, reducing component count and cutting overall hardware cost. • Reduced power draw by ~20% through the consolidated architecture, and improved throttle-response latency by ~21% through control-loop tuning.
Electrical, Electronics and Communications Engineering, Savitribai Phule Pune University
github: https://github.com/Animesh312