---
title: "Anil Gunti - Design Internship in Hyderabad | Tal"
description: "Meet Anil Gunti, Completed Design Verification in VLSI SystemVerilog | UVM | Verification Concepts Open to Entry-Level DV Opportunities and rtl engineer based in Hyderabad."
image: "https://tal.club/meet/anil-gunti/share-image"
---

# Anil Gunti on Tal

## Headline

Completed Design Verification in VLSI SystemVerilog \| UVM \| Verification Concepts Open to Entry\-Level DV Opportunities and rtl engineer

## Location

Hyderabad

## Work experience

Design Internship at Sumedha IT Hyderabad, Oct 2024 \- Oct 2025 · 1 yr 1 mo, Implemented and validated FIFOs using SystemVerilog\. Prototype implementation and verification of APB protocol with System Verilog testbenches\. Involved in RTL verification through SystemVerilog and UVM methodologies\. Implemented testbenches, monitors, scoreboards, functional coverage points and assertions using SystemVerilog, UVM\. Resolved simulation issues and improved verification completeness\. Simulated using EDA tools such as Synopsys VCS, debugged by Verdi\. Gained knowledge on I2C and AXI protocols\.

## Education

Bachelor of Technology \- BTech, Electronic communication engineering, JNTUH College of Engineering Hyderabad

Sree chaitanya high school

[View the original profile](https://tal.club/meet/anil-gunti)

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