Anil Gunti
Completed Design Verification in VLSI SystemVerilog | UVM | Verification Concepts Open to Entry-Level DV Opportunities and rtl engineer
Hyderabad
1+ year of work experience
Oct 20241 yr 1 moOct 2025
Implemented and validated FIFOs using SystemVerilog. Prototype implementation and verification of APB protocol with System Verilog testbenches. Involved in RTL verification through SystemVerilog and UVM methodologies. Implemented testbenches, monitors, scoreboards, functional coverage points and assertions using SystemVerilog, UVM. Resolved simulation issues and improved verification completeness. Simulated using EDA tools such as Synopsys VCS, debugged by Verdi. Gained knowledge on I2C and AXI protocols.
Education
Bachelor of Technology - BTech, Electronic communication engineering
JNTUH College of Engineering Hyderabad
20204 yrs2024
Sree chaitanya high school
20171 yr2018
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