Headline

Associate Director | Semiconductor Engineering Leader | 19 yrs | PDK / CAD | AI & Automation | Multi-Node Enablement | Patents | Publications | Foundry / EDA / SOC Flows | Talent Development

About

Associate Director | Semiconductor Design Enablement | PDK | EDA | PEX | SPICE | PCell | AI & Automation Semiconductor Design Enablement leader with 19 years of experience driving PDK development, qualification, CAD infrastructure, physical verification, and design automation across advanced technology nodes. Currently leading PDK, Parasitic Extraction (PEX), and SPICE-related teams, with deep expertise across DRC/LVS, PEX, SPICE, PCell, EDA integration, CAD automation, and tapeout enablement. Experienced in building scalable, parameter-driven CAD environments and robust multi-model design flows that improve engineering productivity, quality, and reliability across the design ecosystem. Strong focus on automation, AI-driven engineering, and data-driven validation, including AI-based QA methodologies, automated report analysis, intelligent validation frameworks, and productivity flows that accelerate PDK qualification and improve overall design enablement efficiency. Beyond technical execution, passionate about building high-performing engineering teams, developing technical talent, driving cross-functional collaboration, and creating scalable processes and new technology capabilities. Experienced in working across global engineering organizations and aligning technical roadmaps with business and product requirements. An inventor with multiple patents and an author of technical papers presented at EDA and semiconductor forums, with a track record of translating complex engineering challenges into innovative, scalable, and automation-driven solutions. Core Expertise: PDK Development & Qualification | Design Enablement | PEX | SPICE | DRC/LVS | Physical Verification | CAD Infrastructure | EDA Integration | AI/ML for Engineering | Automation | Technical Leadership | High-Performance Teams | Process & Productivity Improvement

Location

Bengaluru

AI stack

claude code

Work experience

Associate Director at Samsung Semiconductor, Mar 2022 - Present · 4 yrs 8 mos, Bengaluru, Karnataka, India, Managing a team of highly motivated engineers to perform PDK PEX (parasitic extraction) component development and UnitQA of all Samsung PDKs including SOC- GAA, FinFet, CMOS, FDSOI, RF, SOI, DDI-Display, CIS-Sensor, BiCMOS, HV, NVM, BCD etc technologies. Developing and driving a coherent Design Enablement EDA strategy to meet the needs of Process Design Kits and Design- Technology Co-optimization on next-generation process technology nodes. Serving as the central Design Enablement contact for both tactical and strategic EDA issues. Identify agendas and concise key messages to achieve Design Enablement strategic directions through executive decisions. Teer development team to standardize development methodology to optimize effectiveness. Close collaboration with EDA vendors to validate PEX tools and improve PEX tool accuracy and usability. CAD flow for Analog/Mix signal Design, PDK, iPDK, Spice simulation, PCells, CDF, Callbacks, techfiles, DRC, ERC, Multiple-patterning, LVS, DFM, post-layout extraction, Metal fill, Layout Finishing & CAD tool development. Collaborating with EDA vendors to enable new design capabilities for PDK. Develop and support parasitic extraction flow (StarRC/Quantus/xRC/xACT) to internal and external customers. Maintaining and customizing design kits and CAD infra-structure on Synopsys/Cadence/Mentor platforms for various process nodes. Driving PDK quality by developing and synthesizing good quality test cases for better coverage. Managing dynamic PDK roadmap and ontime delivery by providing proper sizing and effectively communicating progress and expectations with team members and stakeholders. Pro-eKcient in writing parasitic extraction deck (ITF-StarRC, MIPT-xRC/xACT, ICT-Quantus, PEX map files for model-pex boundary etc). Pro-eKcient in PEX deck accuracy checks, BEOL, MOL, VIAs and Device accuracy analysis. Pro-efficient in pcell (parameterized cells), fluid pcells, FGR PCells development, CDF generation, callbacks & ppf creations.

Senior Manager at Samsung Semiconductor, Mar 2021 - Feb 2022 · 1 yr, Bangalore

Senior Staff Engineer at Samsung Semiconductor, Jun 2018 - Feb 2021 · 2 yrs 9 mos, Bengaluru, Karnataka, India

Staff Design Engineer - PDK at NXP Semiconductors, Aug 2016 - Jun 2018 · 1 yr 11 mos, Noida Area, India, Adept in coordinating across different projects and taking complete ownership of execution of the ongoing projects in terms of deadlines & resources. P-Cells design. Super P-Cells design (Differential Pairs, Current Mirrors, Resistors Ladder, Inverter, NAND, NOR) for CMOS, FDSOI, FinFET, RF, and BCD technologies. PDK integration· Interaction with all stakeholders (designers / global PDK team, foundry representative) to consolidate the PDK requirements. Download and maintain PDK delivery from the foundry. Managing the PDK development and validation plan PDK release for the validation team and final release to the design community. Abstract Generation, VCAR, and VSR support. Integration of PDK-specific Menus and utilities with Cadence design tools. Device enablement (cdf, callbacks, schematic/symbol pcell, view generation). Working with the development/validation team to ensure Quality. Support / enable work management tool for each PDK releases WAM/PIPA · Review of all PDK incoming tickets to get fixed or to provide the correct answer. Enablement for Calibre, PVS tool along with DRC /LVS/ LPE/DFM deck integration flow. Creation of skill-based migration utilities for schematic migration within different technology nodes and maintenance of PDK flow documentation, release notes, foundry documents, PDK deployment guide, etc. Virtuoso layout technology file, layer map files, and display resource files. Generation of technology file, including technology rules, layer properties, layer blockages, constraint groups (VCAR, VSR, VDR), custom vias, routing directions, MPPs devices, FGR pcells etc · Technology LEF to technology file mapping. Generated macro LEF and Antenna LEF Blocks on various technologies. Generation and maintenance of Calibre interactive file for nmDRC, nmLVS, Calibre PERC, Calibre DFM · Calibre layer map file generation. DRC/LVS deck update/modifications as per need of NXP-specific rules. · DRC/LVS regression testing/result comparison for IPs/Chips.

Senior Design Engineer at Freescale Semiconductor, Aug 2008 - Aug 2016 · 8 yrs 1 mo, Noida, § Pro-efficient in pcell (parameterized cells), super pcells, fluid pcells, Fluid Guard Rings PCells development, CDF generation, callbacks and ppf creations. § PCell standardization, PCell migration from CDBA to OA § Device enablement (cdf, callbacks, schematic/symbol pcell, view generation). § Schematic migration from one technology node to other. § Pro-efficient in macro LEF development. § Pro-efficient in library creation and maintenance § Pro-efficient in technology file, map files, display files creation and maintenance. • Enablement for Calibre, PVS tool along with DRC /LVS/ LPE/DFM deck integration flow • Model integration / Simulation setup for spectre, mica, descover, • Helic/VeloceRF enablement • CDL enablement, and models integration • LDE, EAD, MSOT flow enablement • Creation and Maintenance of LAM file for Physical Configuration View in Virtuoso • Creation and Maintenance of chip finishing cells. • Creation and Maintenance of initialization files for Abstract Generation, VCAR, and VSR support. § In depth knowledge & work experience of PDK OA/CDBA format, development & validation methodologies for technologies both in bulk & soi platform such as 250nm, 180nm, 90nm, 65/55nm, 45nm, 40nm, 28nm, 14FinFet § PDK development and Validation experience on both In-house PDKs (NXP/FSL Foundries) and External foundry PDKs (TSMC, Global Foundries, IBM, Samsung, ST, SMIC etc). § Exposure to all functional domains of a Process Design Kit (development and validation) including, simulation, Physical Verification, and technology LEF etc § Detailed exposure to Cadence custom/SOC design tools and Mentor/Cadence physical verification tools. § Intricately involved in providing support to designers for PDK related issues and Enhancements.

ASIC Engineer at QualCore Logic Ltd. (Hyderabad), Sep 2007 - Aug 2008 · 1 yr, Greater Hyderabad Area, Design Layout of Analog Blocks, Digital Blocks, and Standard Cells on TSMC130/180/90/65 nm. Designed the layouts of DLL Digital block, BIAS blocks, DiffAmp, and Current sources using different matching techniques i.e. Common centroid and interdigitated pattern for matching. · Designed the layouts of the Charge Pump and PHFD block and Designed the layouts of Standard cells i.e. Invertor, Logic Gates, Flip-Flops, MUX etc. · Clean LVS, DRC, DFM, and generated RC extraction for BIAS, DiffAmp, PHFD, and Charge Pump. Achievements/Tasks Achievements/Tasks Achievements/Task

Trainee at Sspl, Drdo, New Delhi, Jun 2006 - Aug 2006 · 3 mos, Greater Delhi Area, Study of MEMS fabrication (Lithography) Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through micro fabrication technology.

Education

Bachelor's, Electronics & Communication Engineering, St. Margaret Engineering College, University of Rajasthan

B.E., Electronics and Communication Engg, University of Rajasthan