Aman C.

Bengaluru

Aman C. on Tal

Headline

About

AI enabled- Design Verification Engineer 8+ years of experience in SoC/IP verification EDA & VIP internals, with experience supporting Samsung, STM, Qualcomm, Micron, and SanDisk. Strong expertise in SV, UVM, Verilog, C, Perl, Shell, and Linux, across SPI, I2C, I3C, SMBus, AHB, APB, and AXI. Experienced in developing and debugging SV/UVM environments, functional and toggle coverage, and ARM/ARC-based SoC verification including boot and interrupt flows. Worked directly on VIP and UVM library internals at Synopsys and Cadence, serving as a global technical point of contact for I2C/I3C/SPI VIPs and resolving 800+ customer issues across Broadcom, Qualcomm, NXP, and Meta over 3.5 years. Expert in Professional communication, managing deadlines, task management & prioritization Skills: UVM | SV | SoC Verification | IP Verification | VIP Development | Protocol Verification (I2C/I3C/SPI/AMBA) | Functional & Code Coverage | Debugging (Verdi) | CPUSS| NPUSS | Testbench Architecture | Regression Analysis | Automation (Perl/Shell)

Location

Bengaluru

AI stack

claude code

claude

cursor

gemini

github copilot

githubcopilot

Work experience

DV Lead at Silicon Patterns, Feb 2026 - Present · 8 mos, Bengaluru, Silicon Patterns : DV Team building for SP & on-site client work as below: >On-Client : “SanDisk” “BLR,IND” [2026-Present] Work : SoC-C Verification & Validation * NPUSS connectivity with L1-SRAM & sub-systems like CPUSS, PCI/Host-SS. * NPUSS Clock connectivity and validation * MIPI I3C connectivity check over SoC: * Integration & bring up, A-I3C VIP with SNPS-IP * Updating the I3C Slave device drivers * Porting the existed TCs to current project * Regressions management & Failure analysis

Staff Engineer at Synopsys Inc, Feb 2024 - Jan 2026 · 2 yrs, My Roles and Responsibilities: Enhancement and Support to the VIPs of I2C/I3C/SPI from Synopsys on the VIP based on SV/UVM Helping Customers to setting up Synopsys VIP solutions in their setup, integrate TB in their setup, bring up to tape out of their chip and to market.

SAE at Synopsys Inc, Dec 2022 - Feb 2024 · 1 yr 3 mos, My Roles and Responsibilities: Working On the VIP based on SV/UVM Enhancement and Support Related to SV/UVM based VIPs with Logical, Electrical, Timings and Others available specs based Parameters Supporting issues related to the VIPs of I2C/I3C from Synopsys

SE-II at Cadence Design Systems, Oct 2021 - Dec 2022 · 1 yr 3 mos, Noida, Uttar Pradesh, India, My Roles and Responsibilities: UVM Internal Enhancements and Regressions Analysis (1.1d, 1.2, IEEE and IEEE_ML) UVM Jira's (Functional, RAL and REG_VERIFIER based) Resolution UVM New Edition Library Setup and Test Regression Analysis Resolution Reporting of Regressions Analysis Results and Test Failure analysis to the IEEE Management representative from Cadence UVM IEEE working group.

Senior Engineer at UST, Mar 2021 - Oct 2021 · 8 mos, Bangalore Urban, Karnataka, India, Project details : SoC Based Verification Automation related task like test cleanup for flexible reuse of the files (tests etc) Bring-up of SoC UVM based Environment

Verification Engineer at UST, Jul 2020 - Feb 2021 · 8 mos, Noida, Uttar Pradesh, India, Project details : IP based verification of RCC block using UVM-RAL based by writing test cases/sequence Complete verification matrices Specification and Extraction of V-plan Verification of RCC block with complete verification matrices Integrating v-plan sections wise into V-planner Writing test cases/sequences using UVM Coverage coding and assertion checkers on Simvision/NCSim tool for Coverage IMC Verification plan on V-Planner & Verification Regression Management on V-Manager Git based central repository Test cases like clock switching and interrupt during click switching etc

Verification Engineer I at Incise Infotech Private Limited, Jun 2018 - May 2020 · 2 yrs, Noida, Project Detail 1: TDK invesense Verification of AMBA-APB interconnect Verification of AMBA-AHB based interconnect C based Verification of SPI protocol on ARC 770D SOC System Project Detail 2: C based SoC DV of I2C and SMBUS protocol on ARC based HS-48 SOC System To write C based test cases for I2C and SMBUS protocol for assigned tasks only Test cases like high speed, standard speed, hybrid speed etc Maintaining the 100% toggle coverage for my test cases for I2C and SMBUS using Execution manager Debugging used to be done on Synopsys Verdi Several work related to RTT (Real time trace) for processors, debugging is done during the service Project Detail 3 : Verification of the RPM subsystem based on M3 Controller from ARM Verification of OCM memory connected with various processors available on Chip Migration and Integration of IPCC router that handles the interrupt from one to another processor Managing the changes and reviewing with different teams like Modem, Turing etc before committing Verdi for debugging with execution manager use to manage coverage Achieved the target of 100% toggle coverage for my RPM subsystem QSAM utility and PERSPEC tool from Cadence is used to make Central C based Test generation

Education

i-HUB PG Certificate in VLSI, SoC DV, Indian Institute of Technology, Roorkee

Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, KRISHNA ENGINERING COLLEGE, GHAZIABAD

Aman C.

8+ years of work experience

Aman’s AI Stack

Education