Headline

CAD Engineer | EDA Flow Development, GLS & Functional Verification | Xcelium, Jasper, vManager | 6 Years in VLSI | Open to CAD Engineer Opportunities

About

Built an AI-powered coverage closure solution that delivered a 10X improvement and accelerated critical VLSI verification projects. Over the past 6 years, I've worked across EDA, CAD, verification, and characterization, helping engineering teams solve complex technical problems, automate workflows, and improve verification efficiency. My experience includes debugging and resolving Gate-Level Simulation (GLS) customer issues, reproducing complex failures using targeted testcases, and deploying solutions in customer environments. I've also validated multiple Xcelium features, including Multi-Core execution, RTL accessibility, and SVA accessibility, while working extensively with Xcelium, vManager, IMC, Indago, and Jasper. One of my most impactful projects was developing a Neural Network-based tool that improved coverage closure performance by 10X, helping projects move from 90% to 100% coverage when nightly regressions were no longer hitting new coverbins. The project combined machine learning with practical verification challenges to reduce manual effort and improve engineering productivity. My work also includes implementing Glitch Injection flows, generating glitch destinations using Jasper Superlint and CDC applications, and introducing an ultra-light Perforce client that simplified development workflows for my team. Earlier in my career, I worked on IO and Macro Characterization using Mentor Kronos Characterization and Mentor Solido Characterization Suite. I performed waveform simulations using Mentor Graphics Eldo and used Solido's Anchor Optimizer, Generator, Compare, Validate, Explore, and Leave-One-Out analysis to generate and validate .lib models. In addition to my verification and CAD experience, I write Python scripts to automate engineering tasks and am currently expanding my knowledge in Low Power, UVM, and Physical Design. I'm now seeking opportunities as a CAD Engineer, EDA Engineer, Design Engineer, or R&D Engineer where I can contribute to verification infrastructure, CAD flow development, EDA automation, and next-generation semiconductor solutions. If you're hiring for VLSI CAD, EDA, verification, or design engineering roles, I'd be glad to connect and discuss how my experience can contribute to your team.

Location

Faridabad

AI stack

claude

gemini

notebooklm

openai

Microsoft Copilot

Work experience

Product Engineer II at Cadence Design Systems (India) Pvt. Ltd., Jul 2024 - Present · 2 yrs 3 mos, Noida, Resolved Gate-Level Simulation (GLS) customer issues by analyzing failures, isolating root causes, and delivering validated solutions using Cadence Xcelium. Developed targeted, minimal testcases to reproduce complex customer-reported issues, enabling faster debugging, defect isolation, and effective issue resolution. Supported Xcelium migration activities by investigating compatibility and simulation issues, reproducing failures, and collaborating on reliable migration paths for customer environments. Implemented the Glitch Injection flow by debugging customer-specific issues, validating functionality, and successfully deploying the solution across multiple customer environments. Streamlined the debugging process by creating simplified reproduction scenarios that improved issue analysis, accelerated engineering investigations, and facilitated communication between development and customer support teams.

Engineer, Design Verification Engineering at Analog Devices, Sep 2022 - Jul 2024 · 1 yr 11 mos, Bengaluru, Designed a Neural Network-based solution that delivered a 10X improvement in coverage closure, enabling critical projects to progress from 90% to 100% functional coverage when nightly regressions stopped identifying new coverbins. Developed automation and analysis workflows to improve coverage closure efficiency, combining machine learning techniques with verification methodologies to reduce manual debugging effort. Utilized Cadence Xcelium, vManager, IMC, and Indago to execute simulations, manage regressions, analyze coverage metrics, and debug complex verification issues across VLSI projects. Collaborated with verification engineers to investigate simulation failures, analyze functional coverage, and support efficient regression execution and debug using industry-standard EDA tools.

Product Validation Engineer I at Cadence Design Systems, Oct 2021 - Sep 2022 · 1 yr, Noida, Uttar Pradesh, India, I am working on Xcelium ( a tool of Cadence ) and validating the new features being added in it such as ACCing of ACAs etc . I am also learning about the tools being used in Digital Sign off .

Product Validation Engineer Intern at Cadence Design Systems, Oct 2020 - Sep 2021 · 1 yr, Noida, Uttar Pradesh, India, Validated Xcelium tool for features such as MSIE (Multiple Snapshot incremental Elaboration ) , Accelerated SVA(System Verilog Assertions ) , ACCing in GLS (Gate Level Synthesis ) and RTL (Register Transfer Logic ) Design etc . I have validated Xcelium tool for various platforms such as CentOS , ARM , Solaris and Redhat . Used Indago for debugging Simulation Differences in Signals of Verilog file . I had an idea about ultra light client using Global Perforce Client and implemented this idea in my team .

IO CHARCTERIZATION Intern at STMicroelectronics, Jun 2019 - Dec 2019 · 7 mos, Greater Noida, Uttar Pradesh, India, Performing Characterization for various PVT corners. Timing Views: Non-Linear Delay Modelling [NLDM], Composite Current Source Modelling [ CCS ]. Library Quality, Performance, Reliability Checking. Automation of manual tasks to reduce the overall time & efforts. Implemented Solido on different types of IO’s such as GPIO , I2C , LVDS , SDMMC and SRCNH for NLDM model . Designed Algorithm to implement Solido with Kronos on scratch design .

Verilog Trainee at Truechip Solutions, Jun 2018 - Jul 2018 · 2 mos, Noida, Uttar Pradesh, India, I have learnt basics of Verilog , Linux , Digital Electronics and FPGA I have made a project on SPI protocol .

Education

Bachelor's degree, Electronics and communication, J.C. Bose University of Science and Technology, YMCA

Senior Secondary, Non - Medical, St. Joseph's Convent Sen Sec School - India