Headline

Design Engineer @ Cadence Design systems | Design and Verification Intern @ Synopsys Inc

About

I enjoy working with cutting edge semiconductor technologies which might shape the future. I am into solving design,verification,bring-up deployment and automation related challenges

Location

Bangalore Urban

AI stack

claude code

github copilot

grok

claudecode

Work experience

Design Engineer II at Cadence Design Systems, Mar 2024 - Present · 2 yrs 8 mos, India, Here I work on the top level block.I am responsible for integration of UCIe controllers and the Phy to build the soc Hands on with Jasper Lint ,clock domain crossing and equivalence Checks Worked on Automation Responsible for on time and quality delivery of the package

Design and Verification Intern at Synopsys Inc, Jan 2023 - Feb 2024 · 1 yr 2 mos, Bengaluru, Karnataka, India, Here I am working on DDR Phy Verification.

Teaching Assistant at Indian Institute Of Information Technology, Aug 2021 - Dec 2023 · 2 yrs 5 mos, Prayagraj, Uttar Pradesh, India

Education

Master of Technology - MTech EC, Microelectronics and Vlsi, Indian Institute Of Information Technology allahabad