Headline

FPGA Prototyping Engineer | M Tech in VLSI Design | Ex -Intel | Ex - Vesuvius

About

I’m an M.Tech student specializing in VLSI Design at Amrita Vishwa Vidyapeetham, with a strong foundation in RTL design, functional verification, DFT, static timing analysis (STA), and physical design flow. My engineering journey began in Mechatronics, where I worked hands-on with automation systems and control hardware. This real-world grounding led me into the semiconductor space, where I now work on ASIC/FPGA design, verification, and test methodologies. Core Skills: RTL coding using Verilog & System Verilog Testbench creation, waveform debugging, coverage analysis Scan insertion, ATPG, and logic fault modeling in DFT Physical Design concepts including floor planning, placement, and timing closure Static Timing Analysis and clock tree concepts High-Level Synthesis (HLS) and FPGA prototyping Tools & Platforms: Vivado, ModelSim, Synopsys Design Compiler, Tetramax, Vivado HLS Projects: SVM accelerator using HLS on Basys 3 Edge detection pipeline on Zynq UltraScale+ MPSoC Genetic Algorithm-based ATPG for ISCAS'89 benchmarks SystemVerilog UVM-style testbench for ALU FIR filter with scan chain & PD timing analysis using Synopsys tools I’m actively looking for internship opportunities in RTL Design, Design Verification, DFT, Physical Design, or STA. I’m deeply passionate about building reliable and optimized hardware systems, and I’m eager to contribute to real-world SoC and ASIC development projects. Let’s connect — I’d be happy to collaborate or learn more about your team’s work!

Location

Perintalmanna

AI stack

anthropic apis

claude code

cursor

Work experience

Graduate Technical Intern at Intel Corporation, Aug 2025 - Jul 2026 · 1 yr, Bengaluru, Karnataka, India, •Executed RTL-to-bitstream flows on Synopsys HAPS-100/80 multi-FPGA platforms for pre-silicon validation of IP in a SoC environment. •Performed FPGA prototype deployment and board configuration for system bring-up, validating PCIe and USB interfaces for enumeration and link stability. •Developed and executed validation test suites using Skyhawk and custom Python scripts to verify functional parity of prototyped IP against design specifications. •Collaborated with IP Design teams to debug hardware-level failures during real-time FPGA prototyping, performing signal-level root-cause analysis using Verdi, GTKWave, JTAG, and Metaware Debugger. •Automated implementation/validation workflows with Python and Tcl.

Mechatronics Engineer - Projects at Vesuvius India Ltd, Aug 2022 - Jun 2024 · 1 yr 11 mos, Surat, Gujarat, India, •Diagnosed and resolved failures in automated production systems using systematic signal tracing and electrical troubleshooting, reducing production downtime. •Integrated sensors, PLCs, SCADA, PID controllers, and analog/digital control interfaces into automated systems while maintaining operational and safety requirements. •Developed repeatable system bring-up, troubleshooting, and maintenance procedures and supported site teams in equipment diagnostics and operational reliability.

Intern at Hindustan Aeronautics Limited, Sep 2021 - Oct 2021 · 2 mos, Bangalore Urban, Karnataka, India

Education

Master of Technology - MTech, VLSI Design, Amrita Vishwa Vidyapeetham, Coimbatore

Bachelor of Engineering - BE, Mechatronics, Robotics, and Automation Engineering, Acharya