RTL Design Engineer l llT Bombay ’21 | NIT Trichy ’17 |

Bengaluru

Hybrid

Hyderabad, Telangana, India

India

India




Master's degree, Integrated Circuit Design
Indian Institute of Technology, Bombay

Bachelor's degree, Electronics and Communication
National Institute of Technology, Tiruchirappalli
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Lead Design Engineer at Cadence Design Systems, Jul 2024 - Present · 2 yrs 2 mos, Bengaluru, RTL Design Engineer with expertise in LPDDR5X/LPDDR6 PHY and Testchips design, RTL development, low-power architecture, and design signoff. Experienced in microarchitecture, CDC/RDC, STA, UPF, and silicon bring-up, with a strong background in high-speed semiconductor systems
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Master's degree, Integrated Circuit Design, Indian Institute of Technology, Bombay
Bachelor's degree, Electronics and Communication, National Institute of Technology, Tiruchirappalli