Headline

Physical Verification Engineer @ Samsung | Full-Chip Sign-off (LVS, ERC, DFM, ESD) | 2.5D/3D Advanced Packaging | Building Manufacturable Silicon

About

I'm a Senior Physical Verification Engineer at Samsung Semiconductor, working the last line of defense between a design and the fab: LVS, ERC, PERC, ESD, antenna, density, and DFM sign-off on advanced-node SoCs. I also handle power/bump/IO planning and RDL routing for 2.5D/3D advanced packaging — the physical realities that decide whether a design manufactures cleanly or comes back with an expensive surprise. I help design teams ship silicon that's right the first time — not just checked, but genuinely manufacturable. That means catching issues early, working directly with design and packaging teams instead of throwing reports over a wall, and treating verification as part of building the chip, not just a gate at the end.

Location

India

AI stack

claude code

gemini

Work experience

Senior Engineer at Samsung Semiconductor, Sep 2023 - Present · 3 yrs 1 mo, Bengaluru, Karnataka, India, Physical verification, Power planning, Bump and Io planning, DRC, LVS, DFM, Antenna, density, ESD check ,

Assistant Engineer at Samsung Semiconductor, Oct 2022 - Sep 2023 · 1 yr, Bengaluru, Karnataka, India, Bump planning, RDL Routing, Interposer, 2.5D, 3D, Physical verification,

Education

Singhania University

Diploma, Electrical Engineering, Board of Technical Education Jodhpur