---
title: "Adi Reddy Chinthala - Post Silicon Validation Engineer in Darsi | Tal"
description: "Meet Adi Reddy Chinthala, Curious Mind, M.E Microelectronics(VLSI) @BITS Pilani, Keenly looking for Analog Design/PSV Role. Thank you ! based in Darsi."
image: "https://tal.club/meet/adi-reddy/share-image"
---

# Adi Reddy Chinthala on Tal

## Headline

Curious Mind, M\.E Microelectronics\(VLSI\) @BITS Pilani, Keenly looking for Analog Design/PSV Role\. Thank you \!

## About

Interested in Analog \(Circuits \) Design in particular and Science/Engineering in general\. Worked with the tools Cadence Virtuoso for Analog and Xilinx Vivado\(Verilog\) for digital projects\. Worked in TCS for 1\.5 years as an Assistant Systems Engineer\(software\) and in Cyient Semiconductors as Post silicon validation engineer for more than 1\.7 yrs\. Thank you for your time in showing interest in my profile \!

## Location

Darsi

## Work experience

Post Silicon Validation Engineer at Cyient Semiconductors, Jul 2024 \- Present · 2 yrs 2 mos, Hyderabad, Telangana, India

Intern at Signalchip, Jan 2024 \- Jun 2024 · 6 mos, Bangalore Urban, Karnataka, India

Assistant System Engineer at Tata Consultancy Services, Jun 2018 \- Nov 2019 · 1 yr 6 mos, Greater Hyderabad Area

## Education

Master of Engineering \- M\.E, Microelectronics & VLSI, BITS Pilani, Hyderabad Campus

Bachelor of Technology \- BTech, Electronics& Communication Engineering, Velagapudi Ramakrishna Siddhartha Engineering College

[View the original profile](https://tal.club/meet/adi-reddy)

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