Headline

Entry Level Physical Design Engineer | RTL-to-GDSII | Skilled in EDA Tools (Synopsys DC,FC, ICC2,StarRC,PrimeTime) | STA | Strong in TCL Scripting

About

I am a Trained VLSI Physical Design Engineer with hands-on experience in RTL-to-GDSII flow using Synopsys tools (ICC2, Fusion Compiler, PrimeTime, Design Compiler) on 28nm technology nodes. Skilled in floorplanning, placement, CTS, STA, and power optimization, with strong proficiency in TCL scripting and Linux. Passionate about achieving timing closure, enhancing design performance, and implementing low-power methodologies in advanced semiconductor technologies. Experienced in handling real-time projects involving multi-voltage domains, macro placements, and timing-driven optimizations. Eager to contribute to innovative ASIC and SoC designs while continuously upgrading my skills in next-generation VLSI processes.

Location

Bengaluru

AI stack

claude

codex

deepmind

deepseek

gemini

ChatGPT

Work experience

Physical Design Trainee at VLSIGuru Training Institute, Apr 2025 - Jan 2026 · 10 mos, Bengaluru, Karnataka, India

VLSI Design Engineer at Rooman Technologies, Sep 2024 - Feb 2025 · 6 mos, Bengaluru, Karnataka, India

Education

Bachelor of Engineering - BE, Electronics and communication Engineering, Visvesvaraya Technological University (VTU)

Public links

github: https://github.com/Abhishek-madalli

abhisheksmadalli-protfolio.lovable.app: https://abhisheksmadalli-protfolio.lovable.app/