Headline

Design Verification Engineer @ Pravega Semi | SystemVerilog | UVM | SVA | AMBA | RISC-V | Memory & SoC Verification | GLS | Functional and Code Coverage(IMC)

About

RTL Design & Verification Engineer with ~3 years of hands-on experience in ASIC/SoC RTL design and functional verification using SystemVerilog and Verilog. Experienced in micro-architecture development, synthesizable RTL design, UVM-based verification, assertions (SVA), and debugging of digital IPs and SoC components. Hands-on experience with Cadence tools, including Xcelium/Incisive for simulation and debug, Cadence HAL for linting, Cadence Genus for logic synthesis, Cadence Innovus for PnR and Cadence Conformal for LEC. Worked on Design Verification projects using SystemVerilog, UVM (Universal Verification Methodology), Makefiles, and Python scripting. Familiar with AXI4, AXI-Lite, APB, UART, SPI, I2C, PCIe, CDC/RDC analysis, FSM design, pipelining, and timing-aware RTL development. Open to opportunities in RTL Design, Design Verification (DV), and SoC/IP Verification roles.

Location

Bengaluru

AI stack

codex

cursor

Work experience

Design Engineer at PravegaSemi PVT LTD, Jul 2026 - Present · 2 mos, Bengaluru, Karnataka, India

Associate Member of Technical Staff at DXCorr Design Inc, Aug 2024 - Jul 2026 · 2 yrs, Bengaluru, Karnataka, India

VLSI Engineer at DXCorr Design Inc, Aug 2023 - Aug 2024 · 1 yr 1 mo, Bengaluru, Karnataka, India

Project Trainee at STMicroelectronics, Jun 2022 - May 2023 · 1 yr, Greater Noida, Worked with the IP Packaging & IBIS Modelling Team, My work was based on IP database management and IP Validation using Crossfire(recently changed to Crosscheck).

Education

Master of Technology, Electrical, Electronics and Communications Engineering, National institute of technology delhi

Bachelor of Technology - BTech, Electronics and Communication Engineering, SIEM