Headline

EX-Intern ACLdigital [Physical Design ] | 22nm Design | IEEE member

About

2026 passout BE (ECE) student and Physical Design intern with hands-on experience in the full RTL-to-GDSII flow on 22nm designs using Cadence Innovus and Genus. executed floorplanning, power planning (rings & straps), placement optimization, clock tree synthesis (CTS), routing, and timing ECOs at ACL Digital under Major Project Implemented FFT and multiplier-based DSP blocks in Verilog. Wrote SDC/XDC constraints and debugged timing violations (setup/hold, DRV). Comfortable with TCL scripting for flow automation, report parsing, and constraint generation. Also served as IEEE Sensors Council Treasurer (KSSEM SB), managing finances and coordinating technical events for a 100+ member student branch.

Location

Bengaluru

AI stack

claude

gemini

ollama

perplexity

githubcopilot

ChatGPT

Work experience

Intern at ACL Digital, Jul 2025 - Jun 2026 · 1 yr, Bangalore Urban, Karnataka, India, Physical Design Intern ACL Digital · Internship · Jul 2024 – Present · Bengaluru, Karnataka Working on RTL-to-GDSII implementation of a 22nm design using Cadence Innovus and Genus. Executed floorplanning, power planning (rings/straps), placement, CTS, routing, and post-route timing ECOs. Wrote and verified SDC constraints; debugged setup/hold violations and DRV (max-cap, max-tran) errors.

Education

Bachelor of Engineering, Electrical, Electronics and Communications Engineering, K. S. School Of Engineering and Management

Prarthana School

Public links

github: https://github.com/ABHICHIRU