Headline

Verifying chips @ Infineon | Ex Pixxel

About

I am an experienced Verification and Validation Engineer specializing in the space and semiconductor industries. With a strong foundation in RTL IP core development using UVM and expertise in Xilinx Zynq UltraScale+ MPSoC, I am committed to delivering reliable and high-performance solutions. My work at Pixxel Space includes developing UVM testbenches, validating satellite payload systems, and implementing CI/CD pipelines, all of which have significantly enhanced product efficiency and reliability. I thrive in fast-paced environments, where I leverage my skills in VHDL, Verilog, SystemVerilog, and Python to streamline processes and reduce development cycles.

Location

Bengaluru

AI stack

claude code

github copilot

obsidian

perplexity

ChatGPT

Work experience

Senior Design Verification Engineer at Infineon Technologies, May 2025 - Present · 1 yr 4 mos, Bengaluru, Karnataka, India

Avionics Engineer at Pixxel Space, Jun 2022 - May 2025 · 2 y 11 mo, Bengaluru, Karnataka, India, Check out below link!

Automation Engineer - BMS Automation at EQUANS France, Apr 2021 - Apr 2022 · 1 yr 1 mo, Mumbai, Maharashtra, India, Automatisation des bâtiments Cruise ship SCADA development

Trainee at FutureWiz VLSI Training, Jun 2019 - Jan 2021 · 1 yr 8 mos, Pilani, VLSI Frontend Design and Verification Training. • Learnt writing RTL models in Verilog HDL and Testbenches in System Verilog. • Hands on experience in preparing Verification plans and SV based test benches. • Hands on experience in writing UVM based test benches. • Hands on experience in writing test bench in UVM for AMBA-APB Protocol.

Public Relations Head at IETE Student Forum, May 2018 - Mar 2019 · 11 mos, Public Relations

Education

Bachelor of Technology - BTech, Electronics and Communications Engineering, B K Birla Institute of Engineering & Technology, Pilani

12, Intermediate, Brij Bhushan Lal Public School