---
title: "Abel Joseph John - Associate Engineer in India | Tal"
description: "Meet Abel Joseph John, Putting FPGAs in the cloud based in India."
image: "https://tal.club/meet/abel-joseph/share-image"
---

# Abel Joseph John on Tal

## Headline

Putting FPGAs in the cloud

## Location

India

## Work experience

Associate Engineer at Collins Aerospace, Nov 2023 \- Aug 2026 · 2 yrs 10 mos, \- Avinoics on FPGA

Project Intern \- Design Verification at Collins Aerospace, Aug 2022 \- Nov 2023 · 1 yr 4 mos, – Worked on my Master’s thesis that successfully leveraged AI for the purpose of code coverage prediction in functional verification of RTL designs\.

Engineer \- Verification and Validation at Tata Elxsi, Nov 2020 \- Oct 2021 · 1 yr, Bengaluru, Karnataka, India, – Performed the role of ’Test Architect’ at a German automotive supplier, overseeing validation of the camera system for a Japanese OEM to develop an ADAS system, ensuring ISO26262 and ASPICE compliance\. – Developed the test design for Hardware\-in\-the\-Loop \(HIL\) testing the camera system, and successfully created and executed over 20 tests for verifying the calibration and accuracy of the system on vehicle\. – Led the verification of 2 critical ADAS functions using Model\-in\-the\-Loop \(MIL\) and Software\-in\-the\-Loop \(SIL\) methodod, covering more than 400 requirements\.

Research Intern at VLSI System Design, Jul 2020 \- Sep 2020 · 3 mos, \+ Tools: Magic, ngspice, git, verilog, OSU PDK, Linux \+ Project – Analog PLL using open source tools \+ Used the given RTL verilog code as specification sheet \+ Designed PLL of 8x clock multiplication \(5 MHz to 12\.5 MHz\) using MOSFETs \+ The prelayout simulation was done in ngspcie \+ Targeted the OSU 180nm technology node while doing layout with Magic \+ The layout of all components\(PFD,VCO,charge pump\.\.\) was done in Magic \+ Post layout simulation in ngspice gave 54% duty cycle and 8us settling time \+ Challenge – Limited support for open source tools in VLSI design and lack of additional layers in OSU to make capacitors\. \+ The success of the project was appreciated by Tim Edwards and Timothy Ansell, maintainer of Magic and lead of the open source Sky130 project respectively

Research Intern at Indian Institute of Technology, Madras, Jun 2019 \- Aug 2019 · 3 mos, Chennai, Tamil Nadu, India, \+ Tools: verilog, git, Magic, TCL, shell scripting, Linux \+ Project – Floorplanning for Shakti processor \+ Wrote scripts in TCL for critical portions of chip planning using open source tools \+ The chip die area was calculated based on utilization factor and aspect ratio of core \+ The TCL script reads the standard LEF and the verilog and then calculates the chip area \+ Given the die extensions, the die area is also calculated \+ Cell preplacement was done in the final DEF file \+ The final layout was created in Magic using both DEF and LEF files\. \+ The script was tested on PicoRV32 and Shakti processors \+ Challenge – The tools used could only handle 30,000 cells in each design\. \+ The project was guided by Prof\. V Kamakoti, head of RISE Lab and Shakti development team and Kunal Ghosh

Product Development Intern at Hasura, May 2017 \- Aug 2017 · 4 mos, Bengaluru, Karnataka, India, \- Developed an Android application using Java, Android Studio and the Hasura APIs\. \- Discovered a bug in the user authentication API during app development\.

## Education

Master of Technology \- MTech, Electronics, Digital University Kerala

Bachelor of Technology, Electronics and Communication Engineering, NSS College of Engineering, Palakkad

[View the original profile](https://tal.club/meet/abel-joseph)

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